Publications · the work, written down
What you can
cite.
The architecture and the measurements are documented and publicly registered. We would rather hand you a preprint with a DOI than a slide with a promise.
Technical
preprint.
Registered on Zenodo with a permanent DOI, and submitted to SBESC 2026.
SBESC 2026 · SUBMITTED
Bounding Priority Inversion at IPC Endpoints in an AArch64 Microkernel for Autonomous-Vehicle Control Loops: A Silicon Evaluation on Cortex-A72
Documents the microkernel architecture and the silicon evaluation of priority-inversion containment at IPC endpoints, measured on the Cortex-A72. It does not claim completed certification.
DOI 10.5281/zenodo.20767672Cortex-A72WCETPriority ceiling
Read on Zenodo ↗
The headline
number.
Under induced priority inversion on the bench, with the protection protocol on versus the baseline without it. Measured on the A72, five runs.
2.28 µsprotected IPC under inversion (p99 2351 ns)
~1.003 msbaseline with no inheritance or ceiling
5identical runs
A72silicon, not emulation